The present invention relates to data processing apparatus and, in particular, to memory apparatus for increasing the data processing rate.
Data processing rates continually increase due to advances made at both the logic and the architectural levels of the processing system. Whether considering program storage in main memory or micro-programmed control storage, these advances create an ever increasing demand for higher memory throughputs or, in other words, memory bandwidths. To satisfy this demand, storage space, for example, has been divided into independent, interleaved modules so that, in one memory cycle, the memory system has the potential to service as many requests (i.e., addresses) as there are modules. However, module conflicts occur whenever the same memory module is simultaneously accessed by more than one request. A number of previous studies have shown that memory throughput and processor efficiency can be seriously limited by storage interference. For example, certain studies have shown that, due to memory access conflicts, the average utilization of memory bandwidth of the system grows far less rapidly than the increase in the number of modules. Hellerman in a paper entitled "Digital Computer Systems Principles," McGraw-Hill, New York: 1967, pages 228-229, has demonstrated that M memory modules have a throughput roughly proportional to the .sqroot.M rather than to M itself. Such an inefficient use of bandwidth places a serious restriction on the number of memory modules and the processing rates.
The present invention effectively reduces the prior art limitations by employing the concept of multi-access. In general, the concept refers to the simultaneous, random access of more than one memory location within the same memory module. Physically considered, multi-access consists of independent multiple channels or ports for a single memory module where each port can service a single request in parallel with other ports of the same memory module.
The advantage of multi-access is that the increase in bandwidth utilization is at least directly proportional to the increase in the number of ports. As an example, in a memory structure consisting of an M number of modules with an N an number of independent channels or ports per module, bandwidth utilization of the multi-access system is approximately N times greater than that of the single port structure or, as previously pointed out, it becomes approximately N.sqroot.M.
Another object of the present invention is that it contributes to increase reliability. Since each channel or port is independent of the others, a single channel or port failure no longer forces the faulty module to be excluded from the memory structure. In contrast, in interleaved systems which do not use the multi-channel concept, there is a loss of stored data as well as other problems associated with module loss.